Scalable architecture for word HMM-based speech recognition and VLSI implementation in complete system
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx5/8919/33334/01576887.pdf?arnumber=1576887
Cited by 26 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A Low Power DNN-based Speech Recognition Processor with Precision Recoverable Approximate Computing;2022 IEEE International Symposium on Circuits and Systems (ISCAS);2022-05-28
2. More is Less: Domain-Specific Speech Recognition Microprocessor Using One-Dimensional Convolutional Recurrent Neural Network;IEEE Transactions on Circuits and Systems I: Regular Papers;2021
3. Modified Viterbi Scoring for HMM-based Speech Recognition;Intelligent Automation and Soft Computing;2019
4. Hardware Architectures for Embedded Speaker Recognition Applications;ACM Transactions on Embedded Computing Systems;2017-08-31
5. VLSI Design for SVM-Based Speaker Verification System;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2015-07
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