A 64-Gb/s 0.33-pJ/bit PAM4 Receiver Analog Front-End with a Single-Stage Triple-Peaking CTLE Achieving 22.5-dB Boost in 40-nm CMOS Process
Author:
Affiliation:
1. University of Science and Technology of China
2. Institute of Semiconductors, Chinese-Academy of Sciences
Funder
National Key R&D Program of China
National Natural Science Foundation of China
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10363774/10363775/10364305.pdf?arnumber=10364305
Reference5 articles.
1. A 56-Gb/s 50-mW NRZ Receiver in 28-nm CMOS
2. A 56-Gb/s PAM4 Receiver Analog Front-End With Fixed Peaking Frequency and Bandwidth in 40-nm CMOS
3. A 4.9pJ/b 16-to-64Gb/s PAM-4 VSR transceiver in 28nm FDSOI CMOS
4. An Inverter-Based Analog Front End for a 56 GB/S PAM4 Wireline Transceiver in 16NMCMOS
5. A 32Gb/s wireline receiver with a low-frequency equalizer, CTLE and 2-tap DFE in 28nm CMOS
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