Design Flow for Radhard TMR Flip-Flops
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/7193738/7195649/07195698.pdf?arnumber=7195698
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1. Single Event Transient Reliability Analysis on a Fault-Tolerant RISC-V Microprocessor Design;Lecture Notes in Electrical Engineering;2024
2. RADPlace-MS: A Timing-Driven Placer and Optimiser for ASICs Radiation Hardening;2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT);2022-10-19
3. A Novel Radiation-Hardened CCDM-TSPC Compared with Seven Well-Known RHBD Flip-Flops in 180 nm CMOS Process;Electronics;2022-09-28
4. Laser Fault Injection Attacks against Radiation Tolerant TMR Registers;2022 IEEE 23rd Latin American Test Symposium (LATS);2022-09-05
5. Radiation Tolerant Multi-Bit Flip-Flop System With Embedded Timing Pre-Error Sensing;IEEE Journal of Solid-State Circuits;2022-09
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