A <inline-formula> <tex-math notation="LaTeX">$4\times 5$ </tex-math> </inline-formula>-Gb/s 1.12-<inline-formula> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math> </inline-formula> Locking Time Reference-Less Receiver With Asynchronous Sampling-Based Frequency Acquisition and Clock Shared Subchannels-Reference-Cited by-同舟云学术

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A $4\times 5$ -Gb/s 1.12- $\mu \text{s}$ Locking Time Reference-Less Receiver With Asynchronous Sampling-Based Frequency Acquisition and Clock Shared Subchannels

Published:2016-08 Issue:8 Volume:24 Page:2768-2777
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Song Junyoung,Hwang Sewook,Kim Chulwoo

Funder

National Research Foundation of Korea within the Ministry of Science, ICT, and Future Planning through the Korean Government

MPW of IDEC for fabrication

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx7/92/7519042/07404061.pdf?arnumber=7404061

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 32-Gb/s Dual-Mode Transceiver With One-Tap FIR and Two-Tap IIR RX Only Equalization in 65-nm CMOS Technology;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2021-08

2. A Fully Digital Semirotational Frequency Detection Algorithm for Bang–Bang CDRs;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2019-12

3. Analysis and Verification of Jitter in Bang-Bang Clock and Data Recovery Circuit With a Second-Order Loop Filter;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2019-10

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