ESD/Latch-Up Reliability Enhancements of HV nLDMOSs by Drain-End Horizontally Embedding Different Discrete P+ SCRs
Author:
Affiliation:
1. National United University,Department of Electronic Engineering,Miaoli City,Taiwan,360302
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx8/10547719/10547721/10547995.pdf?arnumber=10547995
Reference5 articles.
1. Design of Bi-Directional ESD Protection Circuit With Uni-Directional ESD Device in BCD Technology
2. Compact Models for Simulation of On-Chip ESD Protection Networks
3. A Novel Segmented LDMOS-SCR Structure With 8-kV HBM ESD Robustness in CMOS Analog Multiplexer
4. Novel SCR Device for ESD Protection with High-Holding Voltage in 0.18um BCD Process
5. Overview on Latch-Up Prevention in CMOS Integrated Circuits by Circuit Solutions
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