A Sub-0.8pJ/b 16.3Gbps/mm<sup>2</sup> Universal Soft-Detection Decoder Using ORBGRAND in 40nm CMOS-Reference-Cited by-同舟云学术

A Sub-0.8pJ/b 16.3Gbps/mm² Universal Soft-Detection Decoder Using ORBGRAND in 40nm CMOS

Published:2023-02-19 Issue: Volume: Page:
ISSN:
Container-title:2023 IEEE International Solid- State Circuits Conference (ISSCC)
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Author:

Riaz Arslan¹,Yasar Alperen¹,Ercan Furkan¹,An Wei²,Ngo Jonathan¹,Galligan Kevin³,Medard Muriel²,Duffy Ken R.³,Yazicigil Rabia Tugce¹

Affiliation:

1. Boston University,Boston,MA

2. Massachusetts Institute of Technology,Cambridge,MA

3. Maynooth University,Maynooth,Ireland

Funder

Defense Advanced Research Projects Agency

Science Foundation Ireland

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10067248/10067251/10067519.pdf?arnumber=10067519

Reference6 articles.

1. A Configurable Successive-Cancellation List Polar Decoder Using Split-Tree Architecture

2. A Fixed Latency ORBGRAND Decoder Architecture With LUT-Aided Error-Pattern Scheduling

3. An Ultra-Low Latency 7.8–13.6 pJ/b Reconfigurable Neural Network-Assisted Polar Decoder with Multi-Code Length Support

4. A 1.1 µs 1.56Gb/s/mm2 Cost-Efficient Large-List SCL Polar Decoder Using Fully-Reusable LLR Buffers in 28nm CMOS Technology;kam;IEEE VLSI Technology and Circuits,2022

5. High-Throughput and Energy-Efficient VLSI Architecture for Ordered Reliability Bits GRAND

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