8.5 A Scalable Adaptive ADC/DSP-Based 1.25-to-56Gbps/112Gbps High-Speed Transceiver Architecture Using Decision-Directed MMSE CDR in 16nm and 7nm-Reference-Cited by-同舟云学术

8.5 A Scalable Adaptive ADC/DSP-Based 1.25-to-56Gbps/112Gbps High-Speed Transceiver Architecture Using Decision-Directed MMSE CDR in 16nm and 7nm

Published:2021-02-13 Issue: Volume: Page:
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Container-title:2021 IEEE International Solid- State Circuits Conference (ISSCC)
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Author:

Xu Danfeng,Kou Yu,Lai Paul,Cheng Zichuan,Cheung Tze Yin,Moser Larry,Zhang Yang,Liu Xiaolong,Lam Man Pio,Jia Haikun,Pan Quan,Szeto Wing Hong,Tang Chi Fai,Mak Ka Fai,Sarfraz Khawar,Zhu Tairan,Kwan Ming,Au Emily Yim Lee,Conroy Cormac,Chan Kai Keung

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9365732/9365735/09366063.pdf?arnumber=9366063

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