Double-Precision FPUs in High-Performance Computing: An Embarrassment of Riches?

Author:

Domke Jens,Matsumura Kazuaki,Wahib Mohamed,Zhang Haoyu,Yashima Keita,Tsuchikawa Toshiki,Tsuji Yohei,Podobas Artur,Matsuoka Satoshi

Publisher

IEEE

Cited by 14 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Mapping Enumeration for Multi-Context CGRAs Using Zero-Suppressed Binary Decision Diagrams;2024 IEEE 32nd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM);2024-05-05

2. At the Locus of Performance: Quantifying the Effects of Copious 3D-Stacked Cache on HPC Workloads;ACM Transactions on Architecture and Code Optimization;2023-12-14

3. Mixed precision support in HPC applications: What about reliability?;Journal of Parallel and Distributed Computing;2023-11

4. Exploration of Compute vs. Interconnect Tradeoffs in CGRAs for HPC;Proceedings of the 13th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies;2023-06-14

5. Less for More: Reducing Intra-CGRA Connectivity for Higher Performance and Efficiency in HPC;2023 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW);2023-05

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