High-precision TDC in an FPGA using a 192 MHz quadrature clock-Reference-Cited by-同舟云学术

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High-precision TDC in an FPGA using a 192 MHz quadrature clock

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Container-title:2002 IEEE Nuclear Science Symposium Conference Record
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Author:

Fries M.D.,Williams J.J.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/8777/27793/01239380.pdf?arnumber=1239380

Cited by 7 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Review of Advancements and Trends in Time-to-Digital Converters Based on FPGA;IEEE Transactions on Instrumentation and Measurement;2024

2. A 128-channel time-to-digital converter based on the 24-phase shift-clock sampling method for RPC;Journal of Instrumentation;2023-02-01

3. 62.5 ps LSB resolution multiphase clock Time to Digital Converter (TDC) implemented on FPGA;Journal of King Saud University - Engineering Sciences;2021-02

4. A high resolution multi-phase clock Time-Digital Convertor implemented on Kintex-7 FPGA;Journal of Instrumentation;2020-11-17

5. The characterization and application of a low resource FPGA-based time to digital converter;Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment;2014-03

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