Design Techniques for Wideband Discrete-Time Delta-Sigma ADCs With Extra Loop Delay-Reference-Cited by-同舟云学术

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Design Techniques for Wideband Discrete-Time Delta-Sigma ADCs With Extra Loop Delay

Published:2011-07 Issue:7 Volume:58 Page:1518-1530
ISSN:1549-8328
Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
language:
Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Wang Yan,Hanumolu Pavan Kumar,Temes Gábor C.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/8919/5934463/05756674.pdf?arnumber=5756674

Cited by 10 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 96 dB DR Second-Order CIFF Delta-Sigma Modulator with Rail-to-Rail Input Voltage Range;Electronics;2024-03-15

2. A Noise-Canceling SMASH Architecture for Discrete-Time Bandpass Delta-Sigma ADCs;2023 IEEE International Symposium on Circuits and Systems (ISCAS);2023-05-21

3. A 72.9-dB SNDR 20-MHz BW 2-2 Discrete-Time Resolution-Enhanced Sturdy MASH Delta–Sigma Modulator Using Source-Follower-Based Integrators;IEEE Journal of Solid-State Circuits;2018-10

4. An Input-Feedforward Delta-Sigma Modulator With Relaxed Timing Constraints;IEEE Transactions on Circuits and Systems II: Express Briefs;2018-03

5. Continuos Time ΣΔ modulator with efficient gain compensated integrators;Microelectronics Journal;2016-10

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