Improved State Integrity of Flip-Flops for Voltage Scaled Retention Under PVT Variation

Author:

Yang Sheng,Khursheed Saqib,Al-Hashimi Bashir M.,Flynn David,Merrett Geoff V.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Minimum SRAM Retention Voltage: Insight about optimizing Power Efficiency across Temperature Profile, Process Variation and Aging;2023 IEEE 29th International Symposium on On-Line Testing and Robust System Design (IOLTS);2023-07-03

2. PVT Aware Analysis of ISCAS C17 Benchmark Circuit;Lecture Notes in Mechanical Engineering;2021

3. Coarse-Grained Online Monitoring of BTI Aging by Reusing Power-Gating Infrastructure;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2017-04

4. Workload Change Point Detection for Runtime Thermal Management of Embedded Systems;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2016-08

5. Design considerations for reliable embedded systems;Reliability Characterisation of Electrical and Electronic Systems;2015

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