A sub-0.85V, 6.4GBP/S/Pin TX-Interleaved Transceiver with Fast Wake-Up Time Using 2-Step Charging Control and V<inf>OH</inf>Calibration in 20NM DRAM Process-Reference-Cited by-同舟云学术

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A sub-0.85V, 6.4GBP/S/Pin TX-Interleaved Transceiver with Fast Wake-Up Time Using 2-Step Charging Control and VOHCalibration in 20NM DRAM Process

Published:2018-06 Issue: Volume: Page:
ISSN:
Container-title:2018 IEEE Symposium on VLSI Circuits
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Author:

Baek Jin-Hyeok,Lee Chang-Kyo,Kim Kiho,Moon Dae-Sik,Cha Gil-Hoon,Heo Jin-Seok,Ahn Minsu,Kim Dong-Ju,Song Jae-Joon,Kwon Seokhong,Kim Jongmin,Kim Kyung-Soo,Ahn Jinoh,Nam Jeong-Sik,Kim Byungcheol,Cho Jeong-Hyeon,Oh Jeong-Hoon,Bae Seung-Jun,Song Indal,Hyun Seok-Hun,Kim Ilgweon,Kwon Hyuck-Joon,Sohn Young-Soo,Choi Jung-Hwan,Park Kwang-Il,Jang Seong-Jin

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8484863/8502213/08502299.pdf?arnumber=8502299

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Theorem on Even Pancyclic Bipartite Digraphs;Mathematical Problems of Computer Science;2021-12-16

2. BIST Architecture for Magnetic Memories;Mathematical Problems of Computer Science;2020-12-25

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