A 0.2GHz to 4GHz Hybrid PLL (ADPLL/Charge-Pump-PLL) in 7NM FinFET CMOS Featuring 0.619PS Integrated Jitter and 0.6US Settling Time at 2.3MW-Reference-Cited by-同舟云学术

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A 0.2GHz to 4GHz Hybrid PLL (ADPLL/Charge-Pump-PLL) in 7NM FinFET CMOS Featuring 0.619PS Integrated Jitter and 0.6US Settling Time at 2.3MW

Published:2018-06 Issue: Volume: Page:
ISSN:
Container-title:2018 IEEE Symposium on VLSI Circuits
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Author:

Tsai Tsung-Hsien,Sheen Ruey-Bin,Chang Chih-Hsien,Staszewski Robert Bogdan

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8484863/8502213/08502274.pdf?arnumber=8502274

Cited by 11 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 4-to-16GHz Dual-Loop PLL Based on Current-Control RO and Calibration in a 6-nm FinFET;2024 13th International Conference on Communications, Circuits and Systems (ICCCAS);2024-05-10

2. Fast Settling Phase-Locked Loops: A Comprehensive Survey of Applications and Techniques [Feature];IEEE Circuits and Systems Magazine;2024

3. A Near-Threshold Ring-Oscillator-Based ILCM with Edge-Selective Error Detector Achieving -64 dBc Reference-Spur and -239 dB FoM;ESSCIRC 2023- IEEE 49th European Solid State Circuits Conference (ESSCIRC);2023-09-11

4. Ring-VCO-based phase-locked loops for clock generation – design considerations and state-of-the-art;Chip;2023-06

5. Design of Low Supply Voltage Phase Locked Loop Based on Dynamic Double Loops Technology;2021 6th International Conference on Integrated Circuits and Microsystems (ICICM);2021-10-22

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