Policy-Based Reinforcement Learning for Through Silicon Via Array Design in High-Bandwidth Memory Considering Signal Integrity-Reference-Cited by-同舟云学术

Policy-Based Reinforcement Learning for Through Silicon Via Array Design in High-Bandwidth Memory Considering Signal Integrity

Published:2024-02 Issue:1 Volume:66 Page:256-269
ISSN:0018-9375
Container-title:IEEE Transactions on Electromagnetic Compatibility
language:
Short-container-title:IEEE Trans. Electromagn. Compat.

Author:

Kim Keunwoo¹^ORCID,Park Hyunwook²^ORCID,Kim Seongguk¹^ORCID,Kim Youngwoo³^ORCID,Son Kyungjune¹^ORCID,Lho Daehwan¹^ORCID,Son Keeyoung¹^ORCID,Shin Taein¹^ORCID,Sim Boogyo¹^ORCID,Park Joonsang¹^ORCID,Park Shinyoung⁴^ORCID,Kim Joungho¹^ORCID

Affiliation:

1. School of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon, South Korea

2. Department of Electrical and Computer Engineering, Missouri University of Science and Technology, Rolla, MO, USA

3. Department of Semiconductor Systems Engineering, Sejong University, Seoul, South Korea

4. Rambus, San Jose, CA, USA

Funder

National R&D Program

National Research Foundation of Korea

Ministry of Science and ICT, South Korea

Samsung

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

http://xplorestaging.ieee.org/ielx7/15/10438898/10403538.pdf?arnumber=10403538

Reference48 articles.

1. Electrical Modeling and Design for 3D System Integration

2. WSPC Series in Advanced Integration and Packaging

3. 3D Packaging Architectures and Assembly Process Design

4. 25.2 A 1.2V 8Gb 8-channel 128GB/s high-bandwidth memory (HBM) stacked DRAM with effective microbump I/O test methods using 29nm process and TSV

5. A 192-Gb 12-High 896-GB/s HBM3 DRAM With a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization

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