Design and realization of sub 100 nm gate length HEMTs-Reference-Cited by-同舟云学术

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Design and realization of sub 100 nm gate length HEMTs

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Container-title:Conference Proceedings. 2001 International Conference on Indium Phosphide and Related Materials. 13th IPRM (Cat. No.01CH37198)
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Author:

Parenty T.,Bollaert S.,Mateos J.,Wallart X.,Cappy A.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/7389/20085/00929234.pdf?arnumber=929234

Cited by 15 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Reduction in interface state density of SiO2/Si-IPL/InP by fluorine and sulfur passivations;Japanese Journal of Applied Physics;2014-11-21

2. Epitaxial Optimization of 130-nm Gate-Length InGaAs/InAlAs/InP HEMTs for High-Frequency Applications;IEEE Transactions on Electron Devices;2008-01

3. Nanometer transistors for emission and detection of THz radiation;Thin Solid Films;2007-03

4. Integration of components in a 50-nm pseudomorphic In0.65Ga0.35As–In0.40Al0.60As–InP HEMT MMIC technology;Solid-State Electronics;2006-05

5. Room-temperature terahertz emission from nanometer field-effect transistors;Applied Physics Letters;2006-04-03

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