Silicon nanowire pinch-off FET : Basic operation and analytical model
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Publisher
IEEE
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http://xplorestaging.ieee.org/ielx5/4832838/4897524/04897582.pdf?arnumber=4897582
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1. Analytical Model for Cylindrical Junctionless Nanowire FETs;2024 IEEE 15th Latin America Symposium on Circuits and Systems (LASCAS);2024-02-27
2. A single-gate SOI nanosheet junctionless transistor at 10-nm gate length: design guidelines and comparison with the conventional SOI FinFET;Journal of Computational Electronics;2020-03-06
3. Charge-Separation Kinetics of Photoexcited Oxygen Vacancies in ZnO Nanowire Field-Effect Transistors;Physical Review Applied;2016-11-28
4. Superior Reliability of Junctionless pFinFETs by Reduced Oxide Electric Field;IEEE Electron Device Letters;2014-12
5. Effect of Geometric Parameters on the Performance of P-Type Junctionless Lateral Gate Transistors;PLoS ONE;2014-04-17
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