Performance analysis: D-Latch modules designed using 18nm FinFET Technology-Reference-Cited by-同舟云学术

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Performance analysis: D-Latch modules designed using 18nm FinFET Technology

Published:2020-09 Issue: Volume: Page:
ISSN:
Container-title:2020 International Conference on Smart Electronics and Communication (ICOSEC)
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Author:

Vallabhuni Rajeev Ratna,Yamini G.,Vinitha T.,Reddy S. Sanath

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9210168/9215228/09215341.pdf?arnumber=9215341

Cited by 20 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Design and Implementation of High-Speed, Low-Power CMOS D Flip-Flop and Counters using Double Gate FinFET Technology;2024 5th International Conference for Emerging Technology (INCET);2024-05-24

2. Gate Electrode Work Function Engineered Nanowire FET with High Performance and Improved Process Sensitivity;Journal of Electronics and Informatics;2024-03

3. Compressive Strength Prediction Model of High Strength Concrete by Destructive and Nondestructive Technique;E3S Web of Conferences;2024

4. Analytical Review on Enhancing Sustainability in microsystems by Integrating MEMS for Compact Design;E3S Web of Conferences;2024

5. CFD Analysis of using Deionized Water in Radiator to Enhance the Efficiency for Sustainable Growth;E3S Web of Conferences;2024

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