Influence of Parasitic Capacitance Variations on 65 nm and 32 nm Predictive Technology Model SRAM Core-Cells

Author:

Carlo Stefano Di,Savino Alessandro,Scionti Alberto,Prinetto Paolo

Publisher

IEEE

Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Behavioral Level Simulation Framework to Support Error-Aware CNN Training with In-Memory Computing;2022 18th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD);2022-06-12

2. Inexact‐aware architecture design for ultra‐low power bio‐signal analysis;IET Computers & Digital Techniques;2016-11

3. TCAD-Assisted Capacitance Extraction of FinFET SRAM and Logic Arrays;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2016-01

4. [Paper] Analysis and Reduction Technologies of Floating Diffusion Capacitance in CMOS Image Sensor for Photon-Countable Sensitivity;ITE Transactions on Media Technology and Applications;2016

5. Memory Test Optimization for Parasitic Bit Line Coupling in SRAMs;2011 Sixteenth IEEE European Test Symposium;2011-05

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