A Versatile Mapping Approach for Technology Mapping and Graph Optimization
Author:
Affiliation:
1. EPFL,Integrated Systems Laboratory,Lausanne,Switzerland
2. Chair for Processor Design, TU Dresden,Dresden,Germany
Funder
German Research Foundation (DFG), project
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9712466/9712479/09712552.pdf?arnumber=9712552
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