A 18.9-22.3GHz Dual-Core Digital PLL with On-Chip Power Combination for Phase Noise and Power Scalability-Reference-Cited by-同舟云学术

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A 18.9-22.3GHz Dual-Core Digital PLL with On-Chip Power Combination for Phase Noise and Power Scalability

Published:2021-06-07 Issue: Volume: Page:
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Container-title:2021 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)
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Author:

Karman Saleh,Tesolin Francesco,Dago Alessandro,Mercandelli Mario,Samori Carlo,Levantino Salvatore

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9489353/9490399/09490476.pdf?arnumber=9490476

Cited by 9 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 0.055 mm2 Total Area Triple-Loop Wideband Fractional-N All-Digital Phase-Locked Loop Architecture for 1.9–6.1 GHz Frequency Tuning;Electronics;2024-07-05

2. A Multireference PLL: Theory and Implementation;IEEE Journal of Solid-State Circuits;2024-07

3. A 6-9.3GHz Low Phase Noise Quad-Core LC VCO in 65nm CMOS;2023 5th International Conference on Circuits and Systems (ICCS);2023-10-27

4. A Compact and Low Phase Noise Square-Geometry Quad-Core Class-F VCO Using Parallel Inductor-Sharing Technique;IEEE Journal of Solid-State Circuits;2023-10

5. A Novel LO Phase-Shifting System Based on Digital Bang-Bang PLLs With Background Phase-Offset Correction for Integrated Phased Arrays;IEEE Journal of Solid-State Circuits;2023-09

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