Minimum SRAM Retention Voltage: Insight about optimizing Power Efficiency across Temperature Profile, Process Variation and Aging
Author:
Affiliation:
1. STMicroelectronics,Crolles,France
2. Univ. Grenoble Alpes/Grenoble INP/CNRS/CEA - IRIG,SPINTEC Laboratory
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10224820/10224858/10224895.pdf?arnumber=10224895
Reference12 articles.
1. Comparing different solutions for testing resistive defects in low-power SRAMs
2. Ultra-Low Standby Power SRAM with Adaptive Data-Retention-Voltage-Regulating Scheme
3. Design of leakage current sensing technique based continues NBTI monitoring sensor using only NMOS
4. An Experimental Evaluation of Resistive Defects and Different Testing Solutions in Low-Power Back-Biased SRAM Cells
5. Improved State Integrity of Flip-Flops for Voltage Scaled Retention Under PVT Variation
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