4-bit CNN Quantization Method With Compact LUT-Based Multiplier Implementation on FPGA-Reference-Cited by-同舟云学术

4-bit CNN Quantization Method With Compact LUT-Based Multiplier Implementation on FPGA

Published:2023 Issue: Volume:72 Page:1-10
ISSN:0018-9456
Container-title:IEEE Transactions on Instrumentation and Measurement
language:
Short-container-title:IEEE Trans. Instrum. Meas.

Author:

Zhao Bingrui¹^ORCID,Wang Yaonan¹^ORCID,Zhang Hui¹^ORCID,Zhang Jinzhou²^ORCID,Chen Yurong¹^ORCID,Yang Yimin³^ORCID

Affiliation:

1. National Engineering Research Center of Robot Visual Perception and Control Technology, School of Robotics, Hunan University, Changsha, China

2. School of Electrical and Information Engineering, Changsha University of Science and Technology, Changsha, China

3. Department of Electrical and Computer Engineering, Western University, London, Canada

Funder

National Natural Science Foundation of China

National Key Research and Development Program of China

Hunan Science Fund for Distinguished Young Scholars

Hunan Key Research and Development Program

Changsha Science and Technology Major Project

Joint Open Foundation of State Key Laboratory of Robotics

China University Industry-University Research Innovation Fund

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Instrumentation

Link

http://xplorestaging.ieee.org/ielx7/19/10012124/10285530.pdf?arnumber=10285530

Reference38 articles.

1. ReActNet: Towards Precise Binary Neural Network with Generalized Activation Functions

2. Fully Quantized Network for Object Detection

3. Small Logarithmic Floating-Point Multiplier Based on FPGA and Its Application on MobileNet

4. Towards accurate and high-speed spiking neuromorphic systems with data quantization-aware deep networks;liu;Proc 55th ACM/ESDA/IEEE Design Autom Conf (DAC),2018

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