High-Speed Configuration Strategy for Configurable Logic Block-Based TCAM Architecture on FPGA

Author:

Ullah Inayat,Afzaal Umar,Ullah Zahid,Lee Jeong-A

Publisher

IEEE

Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Minimizing Subtle Errors in Computing Information of TCAM by Partial “N” Search Key Implementation;International Journal of Uncertainty, Fuzziness and Knowledge-Based Systems;2022-05

2. PackeX: Low-Power High-Performance Packet Classifier Using Memory on FPGAs;Wireless Communications and Mobile Computing;2021-06-07

3. High Performance Power-Efficient Gate-Based CAM for Reconfigurable Computing;2019 15th International Conference on Mobile Ad-Hoc and Sensor Networks (MSN);2019-12

4. Bank-selective Strategy for Gate-based Ternary Content-addressable Memory on FPGAs;2019 IEEE 30th International Conference on Application-specific Systems, Architectures and Processors (ASAP);2019-07

5. DURE: An Energy- and Resource-Efficient TCAM Architecture for FPGAs With Dynamic Updates;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2019-06

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