Scaling of high-k/metal-gate Trigate SOI nanowire transistors down to 10nm width-Reference-Cited by-同舟云学术

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Scaling of high-k/metal-gate Trigate SOI nanowire transistors down to 10nm width

Published:2012-03 Issue: Volume: Page:
ISSN:
Container-title:2012 13th International Conference on Ultimate Integration on Silicon (ULIS)
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Author:

Coquand R.,Barraud S.,Casse M.,Leroux P.,Vizioz C.,Comboroure C.,Perreau P.,Ernst E.,Samson M.-P.,Maffini-Alvaro V.,Tabone C.,Barnola S.,Munteanu D.,Ghibaudo G.,Monfray S.,Boeuf F.,Poiroux T.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/6189092/6193341/06193351.pdf?arnumber=6193351

Cited by 35 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Comprehensive evaluation of gate-induced drain leakage in SOI stacked nanowire nMOSFETs operating in high-temperatures;Solid-State Electronics;2024-02

2. Electrical Characterization of Ω-Gate Nanowire MOSFETs Down to Cryogenic Temperatures;2023 37th Symposium on Microelectronics Technology and Devices (SBMicro);2023-08-28

3. Low-field Mobility Degradation Factors Temperature Dependence in Two-level Stacked Nanowire MOSFETs from 120K to 400K;2023 37th Symposium on Microelectronics Technology and Devices (SBMicro);2023-08-28

4. High Temperature and Width Influence on the GIDL of Nanowire and Nanosheet SOI nMOSFETs;IEEE Journal of the Electron Devices Society;2023

5. Extraction of the Back Channel Mobility in SOI Nanowire MOS Transistors under Substrate Biasing;2022 IEEE Latin American Electron Devices Conference (LAEDC);2022-07-04

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