DDMPs: self-timed super-pipelined data-driven multimedia processors-Reference-Cited by-同舟云学术

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DDMPs: self-timed super-pipelined data-driven multimedia processors

Published:1999 Issue:2 Volume:87 Page:282-295
ISSN:0018-9219
Container-title:Proceedings of the IEEE
language:
Short-container-title:Proc. IEEE

Author:

Terada H.,Miyata S.,Iwata M.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx4/5/15977/00740021.pdf?arnumber=740021

Cited by 20 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. EDA-oriented FPGA Circuit Design Method for Four-phase Bundled-data Circular Self-timed Pipeline;Journal of Information Processing;2023

2. Advantages and disadvantages of using the pointer vector method in a vector dataflow processor;Program Systems: Theory and Applications;2020-12-28

3. Features of Dataflow Processor Emulator Implementing;Lobachevskii Journal of Mathematics;2020-12

4. Pipeline Stage Level Simulation Method for Self-Timed Data-Driven Processor on FPGA;2020 8th International Electrical Engineering Congress (iEECON);2020-03

5. Abnormal Traffic Detection Circuit with Real-time Cardinality Counter;Journal of Information Processing;2018

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