Gate-Lifted nMOS ESD Protection Device Triggered by a p-n-p in Series With a Diode-Reference-Cited by-同舟云学术

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Gate-Lifted nMOS ESD Protection Device Triggered by a p-n-p in Series With a Diode

Published:2019-04 Issue:4 Volume:66 Page:1642-1647
ISSN:0018-9383
Container-title:IEEE Transactions on Electron Devices
language:
Short-container-title:IEEE Trans. Electron Devices

Author:

Lai Da-Wei^ORCID,Sque Stephen^ORCID,Peters Wim,Smedes Theo^ORCID

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx7/16/8668593/08654188.pdf?arnumber=8654188

Cited by 4 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Feedback Enhanced Area-Efficient ESD Power Clamp Circuit;IEEE Transactions on Electron Devices;2024-08

2. Impacts of Floating Poly on Electrostatic Discharge Protection of Power-Managed High-Voltage Laterally Diffused Metal Oxide Semiconductor Components;Electronics;2023-06-25

3. Research on ESD Protection of Ultra-High Voltage nLDMOS Devices by Super-Junction Engineering in the Drain-Side Drift Region;IEEE Journal of the Electron Devices Society;2021

4. Robust and Latch-Up-Immune LVTSCR Device with an Embedded PMOSFET for ESD Protection in a 28-nm CMOS Process;Nanoscale Research Letters;2020-11-11

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