High-Speed SC Decoder for Polar Codes achieving 1.7 Tb/s in 28 nm CMOS-Reference-Cited by-同舟云学术

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High-Speed SC Decoder for Polar Codes achieving 1.7 Tb/s in 28 nm CMOS

Published:2022-10-03 Issue: Volume: Page:
ISSN:
Container-title:2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC)
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Author:

Lopacinski L.¹,Hasani A.¹,Panic G.¹,Maletic N.¹,Gutierrez J.¹,Krstic M.¹,Grass E.¹

Affiliation:

1. IHP – Leibniz-Institut für Innovative Mikroelektronik,Frankfurt Oder,Germany

Funder

Ministry of Education

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9939277/9939284/09939603.pdf?arnumber=9939603

Reference24 articles.

1. A new dimension of parallelism in ultra high throughput LDPC decoding

2. A Hardware Optimized High Throughput LDPC Decoder Supporting 3 Tb/s in 28 nm CMOS;lopacinski;Proc International Symposium on Personal Indoor and Mobile Radio Communications,2022

3. Fully Pipelined Iteration Unrolled Decoders the Road to TB/S Turbo Decoding

4. An overview of channel coding for 5G NR cellular communications

5. A Survey on FEC Codes for 100G and Beyond Optical Networks;tzimpragos;IEEE Communications Surveys & Tutorials,2014

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