A Deterministic Parallel Routing Approach for Accelerating Pathfinder-based Algorithms
Author:
Affiliation:
1. King Fahd University of Petroleum & Minerals,Office of VP for Research & Innovation,Dhahran,Saudi Arabia
2. University of Guelph,Department of Computer Science,Guelph,Canada
3. University of Guelph,School of Engineering,Guelph,Canada
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10321814/10321836/10321904.pdf?arnumber=10321904
Reference16 articles.
1. Titan: Enabling large and complex benchmarks in academic CAD
2. FCRoute: A Fast FPGA Connection Router Using Soft Routing-Space Pruning Algorithm
3. Accelerating FPGA Routing Through Algorithmic Enhancements and Connection-aware Parallelization
4. Timing-Driven Titan
5. Parallel FPGA routing: Survey and challenges;stojilovi?;2017 27th International Conference on Field Programmable Logic and Applications (FPL),2017
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1. A Deterministic Concurrent-Routing Algorithm to Improve Wire Selection in FPGA Routing;2024 9th International Conference on Integrated Circuits, Design, and Verification (ICDV);2024-06-06
2. PatRouter: An Optimal-Pattern-Oriented Routability-Driven Routing Algorithm for FPGA;2024 2nd International Symposium of Electronics Design Automation (ISEDA);2024-05-10
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