Live Demonstration: An Efficient Neural Network Processor with Reduced Data Transmission and On-chip Shortcut Mapping
Author:
Affiliation:
1. Nanjing University,Nanjing,China
Funder
National Key Research and Development Program of China
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10168547/10168548/10168666.pdf?arnumber=10168666
Reference6 articles.
1. A Reconfigurable Streaming Deep Convolutional Neural Network Accelerator for Internet of Things
2. Memory-Efficient CNN Accelerator Based on Interlayer Feature Map Compression
3. A DNN Optimization Framework with Unlabeled Data for Efficient and Accurate Reconfigurable Hardware Inference
4. Flexible-width Bit-level Compressor for Convolutional Neural Network
5. Efficient Hardware Architectures for Deep Convolutional Neural Network
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