Substrate bias effects on drain-induced barrier lowering in short-channel PMOS devices-Reference-Cited by-同舟云学术

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Substrate bias effects on drain-induced barrier lowering in short-channel PMOS devices

Published:1990-07 Issue:7 Volume:37 Page:1707-1713
ISSN:0018-9383
Container-title:IEEE Transactions on Electron Devices
language:
Short-container-title:IEEE Trans. Electron Devices

Author:

Deen M.J.,Yan Z.X.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx1/16/2015/00055758.pdf?arnumber=55758

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