On the Understanding of Defects in Short-Term Negative Bias Temperature Instability (NBTI) for Sub-20-nm DRAM Technology
Author:
Affiliation:
1. National Key Laboratory of Science and Technology on Micro/Nano Fabrication, Shanghai Jiao Tong University, Shanghai, China
2. Institute of Microelectronics, Peking University, Beijing, China
3. ChangXin Memory Technologies, Hefei, China
Funder
National Key Research and Development Program of China
National Natural Science Foundation of China
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
http://xplorestaging.ieee.org/ielx7/55/10132335/10098807.pdf?arnumber=10098807
Reference16 articles.
1. Toward Automated Defect Extraction From Bias Temperature Instability Measurements
2. Impacts of non-negligible electron trapping/detrapping on the NBTI characteristics in silicon nanowire transistors with TiN metal gates;zhang;IEDM Tech Dig,2008
3. Defect level distributions and atomic relaxations induced by charge trapping in amorphous silica
4. Single- Versus Multi-Step Trap Assisted Tunneling Currents—Part I: Theory
5. AC NBTI studied in the 1 Hz -- 2 GHz range on dedicated on-chip CMOS circuits
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