A 0.236 mm$^{2}$, 3.99 mW Fully Integrated 90 nm CMOS L1/L5 GPS Frequency Synthesizer Using a Regulated Ring VCO
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Condensed Matter Physics
Link
http://xplorestaging.ieee.org/ielx5/7260/6210431/06202369.pdf?arnumber=6202369
Cited by 8 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. A Dual Control 3-Stage CSR-VCO with 73.69µW Core Power & -112.25 dBc/Hz Phase Noise with Optimum Area Consumption for RF Applications;2023 26th International Conference on Computer and Information Technology (ICCIT);2023-12-13
2. A Comparative Study of Ring VCO and LC-VCO: Design, Performance Analysis, and Future Trends;IEEE Access;2023
3. The design of low noise broadband navigation satellite receiver frequency synthesizer and the application of BeiDou three generations;International Conference on Algorithms, Microchips and Network Applications;2022-05-06
4. Low power active load and IMOS varactor based VCO designs using differential delay stages in 0.18 μm technology;Microelectronics Journal;2020-04
5. An 18–23 GHz 57.4-fs RMS Jitter −253.5-dB FoM Sub-Harmonically Injection-Locked All-Digital PLL With Single-Ended Injection Technique and ILFD Aided Adaptive Injection Timing Alignment Technique;IEEE Transactions on Circuits and Systems I: Regular Papers;2019-10
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