1. High efficient accurate DL-PO logic multiplier design for low power applications;INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING & COMMUNICATION ENGINEERING SYSTEMS: SPACES-2021;2024
2. Design and Implementation of Booth Multiplier with Sklansky and Ling Adders;Proceedings of the 6th International Conference on Communications and Cyber Physical Engineering;2024
3. Design and Implementation of Optimized FIR Filter using CSA and Booth Multiplier for High Speed Signal Processing;2023 4th International Conference for Emerging Technology (INCET);2023-05-26
4. Analysis of Low-Delay in 64-bit Vedic multiplier based MAC unit;2023 International Conference for Advancement in Technology (ICONAT);2023-01-24
5. PPA Based MAC Unit Using Vedic Multiplier and XOR Logic;Communications in Computer and Information Science;2023