A Scalable Solution to Soft Error Tolerant Circuit Design Using Partitioning-Based Gate Sizing-Reference-Cited by-同舟云学术

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A Scalable Solution to Soft Error Tolerant Circuit Design Using Partitioning-Based Gate Sizing

Published:2017-03 Issue:1 Volume:66 Page:245-256
ISSN:0018-9529
Container-title:IEEE Transactions on Reliability
language:
Short-container-title:IEEE Trans. Rel.

Author:

Sabet M. Amin,Ghavami Behnam,Raji Mohsen

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Safety, Risk, Reliability and Quality

Link

http://xplorestaging.ieee.org/ielx7/24/7867805/07814345.pdf?arnumber=7814345

Cited by 13 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. ReIPE: Recycling Idle PEs in CNN Accelerator for Vulnerable Filters Soft-Error Detection;ACM Transactions on Architecture and Code Optimization;2024-09-14

2. Addressing Single-Event-Multiple-Transient Faults in Asynchronous RH-Click Controllers;2023 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI);2023-08-28

3. SerOpt: Transistor Sizing Algorithm and Optimization Utility for Minimizing Soft Error Rate;2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS);2022-11-16

4. Single Event Transient tolerant Count Min Sketches;Microelectronics Reliability;2022-02

5. General Efficient TMR for Combinational Circuit Hardening Against Soft Errors and Improved Multi-Objective Optimization Framework;IEEE Transactions on Circuits and Systems I: Regular Papers;2021-07

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