Author:
Alpert C.,Kahng A.B.,Bao Liu ,Mandoiu I.,Zelikovsky A.
Cited by
8 articles.
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1. Clock Design and Synthesis;Electronic Design Automation for IC Implementation, Circuit Design, and Process Technology;2016-04-14
2. Revisiting automated physical synthesis of high-performance clock networks;ACM Transactions on Design Automation of Electronic Systems;2013-03
3. A Metal-Only-ECO Solver for Input-Slew and Output-Loading Violations;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2010-02
4. Buffering Interconnect for Multicore Processor Designs;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2008-12
5. Fast Algorithms for Slew-Constrained Minimum Cost Buffering;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2007-11