Minimizing the number of test configurations for FPGAs-Reference-Cited by-同舟云学术

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Minimizing the number of test configurations for FPGAs

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Container-title:IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.
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Author:

Chmelar E.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/9494/30133/01382702.pdf?arnumber=1382702

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Evaluation of the SEU Faults Coverage of a Simple Fault Model for Application-Oriented FPGA Testing;2020 23rd Euromicro Conference on Digital System Design (DSD);2020-08

2. A Routability-Aware Algorithm for Both Global and Local Interconnect Resource Test and Diagnosis of Xilinx SRAM-FPGAs;Journal of Electronic Testing;2016-11-09

3. Development of At-speed Interconnect Test to Capture Marginal Open Defect on FPGA;9th International Conference on Robotic, Vision, Signal Processing and Power Applications;2016-09-30

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