FL-RuNS: A High-Performance and Runtime Reconfigurable Fault-Tolerant Routing Scheme for Partially Connected Three-Dimensional Networks on Chip
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Computer Science Applications
Link
http://xplorestaging.ieee.org/ielx7/7729/8599030/08782834.pdf?arnumber=8782834
Cited by 8 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Congestion-Aware Vertical Link Placement and Application Mapping Onto 3-D Network-on-Chip Architectures;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2024-08
2. AdEle+: An Adaptive Congestion-and-Energy-Aware Elevator Selection for Partially Connected 3D Networks-on-Chip;IEEE Transactions on Computers;2023-08-01
3. Design of a Fault-Tolerant Pseudo-3D Routing;2023 IEEE International Test Conference India (ITC India);2023-07-23
4. AdEle: An Adaptive Congestion-and-Energy-Aware Elevator Selection for Partially Connected 3D NoCs;2021 58th ACM/IEEE Design Automation Conference (DAC);2021-12-05
5. Reflect3d: An Adaptive and Fault-Tolerant Routing Algorithm for Vertically-Partially-Connected 3D-NoC;2021 34th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI);2021-08-23
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