FDSOI bottom MOSFETs stability versus top transistor thermal budget featuring 3D monolithic integration

Author:

Fenouillet-Beranger C.,Previtali B.,Batude P.,Nemouchi F.,Casse M.,Garros X.,Tosti L.,Rambal N.,Lafond D.,Dansas H.,Pasini L.,Brunet L.,Deprat F.,Gregoire M.,Mellier M.,Vinet M.

Publisher

IEEE

Cited by 14 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Design-Technology Co-Optimization for Stacked Nanosheet Oxide Channel Transistors in Monolithic 3D Integrated Circuit Design;IEEE Transactions on Nanotechnology;2024

2. Efficient and Scalable MIV-Transistor with Extended Gate in Monolithic 3D Integration;2023 IEEE 66th International Midwest Symposium on Circuits and Systems (MWSCAS);2023-08-06

3. Metal Inter-layer Via Keep-out-zone in M3D IC: A Critical Process-aware Design Consideration;2023 24th International Symposium on Quality Electronic Design (ISQED);2023-04-05

4. Optimization of solid-phase epitaxial regrowth performed by UV nanosecond laser annealing;MRS Advances;2022-12-21

5. A monolithic 3D design technology co-optimization with back-end-of-line oxide channel transistor;Proceedings of the 17th ACM International Symposium on Nanoscale Architectures;2022-12-07

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