Implementation of Multiple Kernels for Edge Detection using Pipelined Architecture on FPGA
Author:
Affiliation:
1. SRM Institute of Science and Technology Kattankulathur,Department of Electronics and Communication Engineering,Chennai,India,603 203
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10156871/10156874/10157557.pdf?arnumber=10157557
Reference12 articles.
1. Acute lymphoblastic leukemia (ALL) image dataset;aria;Kaggle,2021
2. Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks
3. Area Efficient FPGA Implementation of Sobel Edge Detector for Image Processing Applications
4. Snowflake: A Model Agnostic Accelerator for Deep Convolutional Neural Networks;gokhale;ArXiv Preprint,2017
5. Edge dedection application with FPGA based Sobel operator
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