Challenges of Cu CMP of TSVs and RDLs fabricated from the backside of a thin wafer-Reference-Cited by-同舟云学术

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Challenges of Cu CMP of TSVs and RDLs fabricated from the backside of a thin wafer

Published:2013-10 Issue: Volume: Page:
ISSN:
Container-title:2013 IEEE International 3D Systems Integration Conference (3DIC)
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Author:

Chen Jui-Chin,Lau John H.,Hsu Tzu-Chien,Chen Chien-Chou,Tzeng Pei-Jer,Chang Po-Chih,Chien Chun-Hsien,Chang Yiu-Hsiang,Chen Shang-Chun,Hsin Yu-Chen,Liao Sue-Chen,Lin Cha-Hsin,Ku Tzu-Kun,Kao Ming-Jer

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/6690582/6702313/06702335.pdf?arnumber=6702335

Cited by 5 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Novel Single and Co-Ion Implantation Induced Backside Etch Stop Structures for 3D Multilayer Stacked Package;2024 IEEE 74th Electronic Components and Technology Conference (ECTC);2024-05-28

2. Recent Advances and Trends in Multiple System and Heterogeneous Integration With TSV Interposers;IEEE Transactions on Components, Packaging and Manufacturing Technology;2023-01

3. Multiple System and Heterogeneous Integration with TSV-Interposers;Chiplet Design and Heterogeneous Integration Packaging;2023

4. 2.5D IC Integration;Semiconductor Advanced Packaging;2021

5. A Novel Method for Air-Gap Formation around Via-Middle (VM) TSVs for Effective Reduction in Keep-Out Zones (KOZ);2017 IEEE 67th Electronic Components and Technology Conference (ECTC);2017-05

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