Gate-Last I/O Transistors based on Stacked Gate-All-Around Nanosheet Architecture for Advanced Logic Technologies-Reference-Cited by-同舟云学术

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Gate-Last I/O Transistors based on Stacked Gate-All-Around Nanosheet Architecture for Advanced Logic Technologies

Published:2021-12-11 Issue: Volume: Page:
ISSN:
Container-title:2021 IEEE International Electron Devices Meeting (IEDM)
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Author:

Bhuiyan M.¹,Kim M.²,Zhou H.¹,Lo H.²,Siddiqui S.¹,Stolfi M.²,Guarini T.²,Pujari R.¹,Davey E.²,Stuckert E.¹,Li J.¹,Chou A.¹,Zhao K.¹,Wang M.¹,Guo D.¹,Colombeau B.²,Loubet N.¹,Haran B.²,Bu H.¹

Affiliation:

1. IBM Research,Albany,NY,USA

2. Applied Materials,Sunnyvale,CA,USA

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9720433/9720494/09720507.pdf?arnumber=9720507

Reference7 articles.

1. Performance dependence of CMOS on silicon substrate orientation for ultrathin oxynitride and HfO2 gate dielectrics

Cited by 4 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 1.8-V GPIO With Design-Technology-Reliability Co-Optimization in Sub-3-nm GAA-NS Technology;IEEE Journal of Solid-State Circuits;2024

2. A Low-Temperature SiO2 Interfacial Layer Preparation using Rapid Thermal Oxidation Process for GAA Nanosheet Based I/O Transistor;Silicon;2023-11-29

3. Stacked Lateral Gate-All-Around Metal–Oxide–Semiconductor Field-Effect Transistors and Their Three-Dimensional Integrated Circuits;Silicon;2022-10-29

4. Co-integration Process Compatible Input/Output (I/O) Device Options for GAA Nanosheet Technology;ESSDERC 2022 - IEEE 52nd European Solid-State Device Research Conference (ESSDERC);2022-09-19

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