Drain Current Degradation Induced by Charge Trapping/De-Trapping in Fe-FET-Reference-Cited by-同舟云学术

Drain Current Degradation Induced by Charge Trapping/De-Trapping in Fe-FET

Published:2024-04-14 Issue: Volume: Page:P6.EM-1-P6.EM-4
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Container-title:2024 IEEE International Reliability Physics Symposium (IRPS)
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Author:

Kim Taeyoung¹,Lim Suhwan¹,Myeong Ilho¹,Park Sanghyun¹,Noh Suseong¹,Lee Seung Min¹,Woo Jongho¹,Ko Hanseung¹,Noh Youngji¹,Choi Moonkang¹,Lee Kiheun¹,Han Sangwoo¹,Baek Jongyeon¹,Kim Kijoon¹,Jung Dongjin¹,Kim Ji-sung¹,Park Jaewoo¹,Kim Seunghyun¹,Kim Hyoseok²,Yoo Sijung³,Lee Hyun Jae³,Choe Duk-Hyun³,Nam Seung-Geol³,Yoon Ilyoung¹,Kim Chaeho¹,Kim Kwanzsoo¹,Park Kwanzmin¹,Kuh Bong Jin¹,Heo Jinseong³,Kim Wanki¹,Ha Daewon¹,Song Jaihyuk¹

Affiliation:

1. Semiconductor R&D Center, South Korea,Hwaseong-si,Gyeonggi-do,South Korea

2. Innovation Center, Samsung Electronics Co., Ltd, South Korea,Hwaseong-si,Gyeonggi-do,South Korea

3. Samsung Advanced Institute of Technology, South Korea,Hwaseong-si,Gyeonggi-do,South Korea

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10529283/10529298/10529466.pdf?arnumber=10529466

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4. Memory Window Expansion for Ferroelectric FET based Multilevel NVM: Hybrid Solution with Combination of Polarization and Injected Charges

5. Comprehensive Design Guidelines of Gate Stack for QLC and Highly Reliable Ferroelectric VNAND