A Novel Induced Offset Voltage Sensor for Separable Wear-Out Mechanism Characterization in a 12nm FinFET Process
Author:
Affiliation:
1. University of British Columbia,Department of Electrical and Computer Engineering,Vancouver,Canada
Funder
NSERC
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10529283/10529298/10529475.pdf?arnumber=10529475
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1. CMOS Reliability from Past to Future: A Survey of Requirements, Trends, and Prediction Methods
2. The Changing Automotive Environment: High-Temperature Electronics
3. A Versatile CMOS Transistor Array IC for the Statistical Characterization of Time-Zero Variability, RTN, BTI, and HCI
4. Reliability studies of a 32nm System-on-Chip (SoC) platform technology with 2nd generation high-k/metal gate transistors
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