Logic synthesis method for combinatorial blocks using a FPGA-like basic cell structure
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Published:2015-10
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Container-title:2015 19th International Conference on System Theory, Control and Computing (ICSTCC)
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Author:
Monor Calin-Mircea
Cited by
1 articles.
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1. A Topology-flattening-based Automated Incremental Synthesis Method;2024 2nd International Symposium of Electronics Design Automation (ISEDA);2024-05-10