A Scalable Methodology for Designing Efficient Interconnection Network of Chiplets

Author:

Feng Yinxiao1,Xiang Dong2,Ma Kaisheng1

Affiliation:

1. Tsinghua University,Institute for Interdisciplinary Information Sciences (IIIS),Beijing,China

2. Tsinghua University,School of Software,Beijing,China

Publisher

IEEE

Reference55 articles.

Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. NxtSPR: A deadlock-free shortest path routing dedicated to relaying for Triplet-Based many-core Architecture;Parallel Computing;2024-09

2. AdCoalescer: An Adaptive Coalescer to Reduce the Inter-Module Traffic in MCM-GPUs;Proceedings of the 53rd International Conference on Parallel Processing;2024-08-12

3. Designing Reconfigurable Interconnection Network of Heterogeneous Chiplets Using Kalman Filter;Proceedings of the Great Lakes Symposium on VLSI 2024;2024-06-12

4. Modeling methodology for multi-die chip design based on gem5/SystemC co-simulation;Proceedings of the 16th Workshop on Rapid Simulation and Performance Evaluation for Design;2024-01-18

5. M2M: A Fine-Grained Mapping Framework to Accelerate Multiple DNNs on a Multi-Chiplet Architecture;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024

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