AutoCAT: Reinforcement Learning for Automated Exploration of Cache-Timing Attacks

Author:

Luo Mulong1,Xiong Wenjie2,Lee Geunbae2,Li Yueying1,Yang Xiaomeng3,Zhang Amy3,Tian Yuandong3,Lee Hsien-Hsin S.4,Suh G. Edward1

Affiliation:

1. Cornell University

2. Virginia Tech

3. Meta AI

4. Intel Corporation

Publisher

IEEE

Reference86 articles.

1. Real time detection of cache-based side-channel attacks using hardware performance counters

2. Reinforcement learning-based design of side-channel countermeasures;rijsdijk;Cryptology ePrint Archive Report,2021

3. Leaking control flow information via the hardware prefetcher;chen,2021

4. Deep reinforcement learning approach for autonomous vehicle systems for maintaining security and safety using LSTM-GAN

5. A Benchmark Suite for Evaluating Caches' Vulnerability to Timing Attacks

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1. Uncovering and Exploiting AMD Speculative Memory Access Predictors for Fun and Profit;2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA);2024-03-02

2. One more set: Mitigating conflict-based cache side-channel attacks by extending cache set;Journal of Systems Architecture;2023-11

3. Uncore Encore: Covert Channels Exploiting Uncore Frequency Scaling;56th Annual IEEE/ACM International Symposium on Microarchitecture;2023-10-28

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