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A High Performance and Memory Efficient LU Decomposer on FPGAs

  • Published:2012-03 Issue:3 Volume:61 Page:366-378
  • ISSN:0018-9340
  • Container-title:IEEE Transactions on Computers
  • language:
  • Short-container-title:IEEE Trans. Comput.

Author:

Wu Guiming,Dou Yong,Sun Junqing,Peterson Gregory D.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Computational Theory and Mathematics,Hardware and Architecture,Theoretical Computer Science,Software

Cited by 23 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Analysis and Optimization of Block LU Decomposition for Execution on Tightly Coupled Processor Arrays;2024 IEEE 35th International Conference on Application-specific Systems, Architectures and Processors (ASAP);2024-07-24

2. A Modified Strassen Algorithm based DSP Accelerated 3D Kalman Filter;2023 IEEE 12th International Conference on Communication Systems and Network Technologies (CSNT);2023-04-08

3. Multi-FPGA Designs and Scaling of HPC Challenge Benchmarks via MPI and Circuit-switched Inter-FPGA Networks;ACM Transactions on Reconfigurable Technology and Systems;2023-03-11

4. FPGA Implementation of Tri-matrix Multiplication Accelerator using Circulant Matrices for Kalman Filters;2022 IEEE 2nd Mysore Sub Section International Conference (MysuruCon);2022-10-16

5. Realization and Optimization of Inverse Algorithm of QR Decomposition of Arbitrary Order Signal Autocorrelation Matrix Based on HLS;2021 CIE International Conference on Radar (Radar);2021-12-15
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