Design of a 12-bit 0.83 MS/s SAR ADC for an IPMI SoC-Reference-Cited by-同舟云学术

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Design of a 12-bit 0.83 MS/s SAR ADC for an IPMI SoC

Published:2015-09 Issue: Volume: Page:
ISSN:
Container-title:2015 28th IEEE International System-on-Chip Conference (SOCC)
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Author:

Zhou Han,Gui Xiaoyan,Gao Peng

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/7363404/7406870/07406935.pdf?arnumber=7406935

Cited by 9 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. An 8 bit-ENOB Sampling-rate Reconfigurable Asynchronous SAR ADC with Metastability Watchdog Circuit for Activity-driven Multi-Channel CMOS Readout ASICs for Space Applications;AEU - International Journal of Electronics and Communications;2024-01

2. Methods to Improve Linearity of Signal’s Analog-to-Digital Conversion with Self-Calibration;Machine Learning-based Design and Optimization of High-Speed Circuits;2023-12-31

3. 1-kS/s 12-bit SAR ADC with Burst Conversion;2023 20th International SoC Design Conference (ISOCC);2023-10-25

4. 1^st-Order Error-Feedback Sampling-Rate Reconfigurable Noise-Shaping SAR ADC for Multi-Channel CMOS Front-End ASICs for Space Applications;2023 21st IEEE Interregional NEWCAS Conference (NEWCAS);2023-06-26

5. An 11-Bit 10 MS/s SAR ADC with C–R DAC Calibration and Comparator Offset Calibration;Electronics;2022-11-09

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