A Review on Implementation of AES Algorithm Using Parallelized Architecture on FPGA Platform-Reference-Cited by-同舟云学术

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A Review on Implementation of AES Algorithm Using Parallelized Architecture on FPGA Platform

Published:2023-04-29 Issue: Volume: Page:
ISSN:
Container-title:2023 IEEE International Conference on Advanced Systems and Emergent Technologies (IC_ASET)
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Author:

Mohammed Nada Qasim¹,Amir Amiza¹,Ahmad Badlishah¹,Salih Muataz Hammed²,Arrfou Hana³,Thalji Nisrean⁴,Matem Rema,Abbas Jamal Kamil K.⁵,Hussien Qasim Mohammed⁵,Abdulhassan Maki Mahdi⁵

Affiliation:

1. University Malaysia Perlis,Electronic Engineering & Technology,Arau,Malaysia,02600

2. Design and Engineering, Flex,Automation Group,Penang,Malaysia,11500

3. College of Qatar,Business administration,Doha,Qatar,122104

4. Jadara University,Robotics and Artificial Intelligence,Irbid,Jordan

5. Al-Nisour University College,Computer Engineering Techniques,Baghdad,Iraq,10036

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10149846/10150436/10150938.pdf?arnumber=10150938

Reference36 articles.

1. Design and implementation image processing functional unit using spatial parallelism on FPGA;mohammed;ARPN Journal of Engineering and Applied Sciences,0

2. A low area high speed FPGA implementation of AES architecture for cryptography application;thanikodi manoj;Electronics,2021

3. FPGA implementation of hardware architecture with AES encryptor using sub-pipelined S-box techniques for compact applications

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