Low-power, high-performance 64-bit CMOS priority encoder using static-dynamic parallel architecture
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/7492613/7495097/07495160.pdf?arnumber=7495160
Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Gate-Level Hardware Priority Resolvers for Embedded Systems;Journal of Low Power Electronics and Applications;2024-04-17
2. Architectural analysis of 1-D to 2-D array conversion of priority encoder;International Journal of System Assurance Engineering and Management;2023-07-04
3. Architectural Improvement and Performance Evaluation of 1D-to-2D Array Conversion Priority Encoder;2022 International Conference on Smart Generation Computing, Communication and Networking (SMART GENCON);2022-12-23
4. A Novel low power 2-D to 3-D Array Priority Encoder using Split-Logic Technique for Data Path Applications;WSEAS TRANSACTIONS ON SYSTEMS AND CONTROL;2022-01-07
5. Low power high performance priority encoder using 2D-array to 3D-array conversion;Procedia Computer Science;2020
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